As technology in products and equipment continue to become more complex, the use of integrated circuit (IC) devices in these products and equipment is basically essential. In addition, consumers and manufacturers alike have continued to desire smaller product size, which requires a continued decrease in overall IC chip size. As a result, the large-scale integration of circuit components, such as transistors and capacitors, has become a necessity for decreased overall size, but increased device performance. Thus, semiconductor device improvements have been largely accomplished by reducing device feature size to the point where currently micron and sub-micron device features are being used, and predictions for future device sizes do not foresee an end to the trend of ever smaller and denser devices.
Along with desired reductions in device size, and thus increased chip densities, comes a required reduction in device power consumption that imposes the use of decreased device feature lengths. This is because, as a general rule, device speed varies inversely with device feature length, while power consumption increases approximately with the square of the device feature length. Thus, feature sizes currently being employed are in the micron and sub-micron or 0.5 um range where it is not considered impossible that the feature size of 0.2 um will become a reality in the near future.
Field Effect Transistors (FETs) are at this time used extensively in Ultra Large-Scale Integration (ULSI) applications. FETs are formed using gate electrodes, usually made of polysilicon, over a gate oxide, and adjacent source/drain regions surrounding the gate oxide to define the channel of the device. In the face of reduced device sizes, contact pads are typically employed in the source/drain regions, and over the gate electrode, to improve the electrical connection between the parts of the transistor and metal interconnects dispersed throughout the IC chip to connect circuit components. These contact pads are typically comprised of a metal silicide formed by reacting a deposited metal with the polysilicon it is deposited over. However, reduced device size effectively translates into reduced contact pad size, and it therefore becomes more critical that the electrical connection between the metal interconnects and the silicide pads be strong since the contact area between the two is reduced as well.
Metal silicide has been employed to provide the electrical contact between parts of the semiconductor devices and these metal interconnects primarily because of the reduced contact resistance and sheet resistance provided by metal silicide. However, one of the most significant factors that can impact the strength of the electrical connection between the silicide pads and the metal interconnects (e.g., increased contact and sheet resistance) is oxidation of the metal silicide before the metal interconnect contacting the silicide is formed. This is due to the oxidation of metals when they are exposed to an oxygen-containing environment, and typically the longer the exposure, the more oxide that is formed. Since semiconductor wafers are typically mass-produced, delays in the manufacturing process often leave wafers “in queue,” awaiting the next step of the manufacturing process, and queue times of several days are not uncommon.
Thus, if metal silicide pads have been formed but that wafer is put in queue while the metal silicide portions are exposed, those exposed portions begin to oxidize. Of course, the longer the wafer(s) stays in queue awaiting the next step in the manufacturing process, the more oxidation of the silicide takes place. Then, when the awaiting wafer finally reaches the point in the process where the metal interconnects (i.e., metal “plugs”) are formed in contact with silicide pads, the oxidized surfaces of the silicide pads detrimentally affect this electrical connection. Specifically, both the contact resistance and sheet resistance of the metal silicide pads are impacted, which results in reduced stability in the electrical connections, and thus a reduction in device performance. Accordingly, what is needed is a technique for reducing or eliminating the oxidation of exposed metal silicide in semiconductor wafers when those wafers are held in queue during the manufacturing process.